Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
An FPGA configurable logic block (CLB) typically includes one or more groups of related lookup tables and memory elements. The lookup tables (LUTs) are related to one another in that the LUT output signals are coupled to a common carry chain, and the memory elements are typically also related in that each can be optionally driven by the output signal from one of the LUTs. Such a group of logic is commonly known as a “slice”. For example, FIGS. 6A and 6B of U.S. Pat. No. 5,914,616 each illustrate one slice from the well-known Virtex™ FPGA currently available from Xilinx, Inc. (U.S. Pat. No. 5,914,616 is hereby incorporated herein by reference in its entirety.) Together, these two slices make up one CLB of the Virtex FPGA.
In order to reduce the number of transistors required to implement a slice, the memory elements within a slice typically share common control signals, e.g., clock, clock enable, set, and/or reset signals. Because the user logic implemented in a slice is often related, the logic targeted to memory elements within one slice can typically share common control signals without significant loss of implementation efficiency.
FIG. 1 shows how memory elements share control signals in a known FPGA, the Virtex-II Pro™ FPGA from Xilinx, Inc. (FIG. 1 is derived from a figure on page 51 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Dr., San Jose, Calif., which page is hereby incorporated herein by reference.) In the Virtex-II Pro PFGA, each slice includes two memory elements, each configurable as either a latch or a flip-flop. As shown in FIG. 1, memory elements FFX and FFY in each slice share common clock (CK), clock enable (CkE), and S/R (set/reset) signals.
More specifically, memory element FFX has a data input terminal Dt driven by a data input multiplexer 102, which selects between data input DX and a bypass data input BX (optionally inverted by programmable multiplexer 115). Memory element FFY has a data input terminal D driven by a data input multiplexer 101, which selects between data input DY and a bypass data input BY (optionally inverted by programmable multiplexer 111). The clock enable (CkE) input terminal of each memory element FFX, FFY is driven by a clock enable signal CE optionally inverted by multiplexer 112. The clock (CK) input terminal of each memory element FFX, FFY is driven by a clock signal CLK optionally inverted by multiplexer 113. The set/reset (S/R) input terminal of each memory element FFX, FFY is driven by a set/reset signal SR optionally inverted by multiplexer 114. The reverse set/reset (REV) input terminal of each memory element FFX, FFY is optionally driven (as controlled by programmable switches 122, 121, respectively) by the bypass signal BY optionally inverted by multiplexer 111.
In the Virtex-II Pro slice, some programmable attributes for the memory elements apply to both memory elements in the slice, while others are individually controllable for each memory element. For example, the following attributes are specific to each flip-flop: INIT0 (initialize to a low value); INIT1 (initialize to a high value); SRHIGH (signal S/R sets the value in the memory element; signal REV resets the value); and SRLOW (signal S/R resets the value in the memory element; signal REV sets the value). However, if synchronous functionality is selected for the slice, this selection applies to both memory elements. Similarly, a selection of asynchronous functionality applies to both memory elements.
Power consumption is an important consideration for PLD systems designers. Particularly with today's larger PLDs, power consumption can be such a critical issue that it can dictate the choice of whether or not a given PLD can be used to implement a particular user design. Therefore, it is desirable to find methods of reducing power consumption in PLDs. Because many available PLDs include thousands of programmable memory elements, programmable memory elements having reduced power consumption could provide a significant power savings over currently available circuits.